1. Field of the Invention
The invention relates to the field of semiconductor fabrication and, more particularly, to a transistor having extremely shallow source/drain junction depths and a method for fabricating the transistors.
2. Description of the Related Art
Integrated circuits are widely used in the electronics industry for an extremely broad range of applications including microprocessors, integrated circuit memories, and application specific logic products. The basic building block of the integrated circuit is the MOS transistor. FIG. 10 shows a typical embodiment of a single MOS n-channel transistor. MOS transistor 10 includes a lightly doped p-type semiconductor substrate 12 a gate dielectric 16 formed on substrate 12, a conductive gate 14 formed on gate dielectric 16, n-type source region 18, and n-type drain region 20. The operation and I-V characteristics of transistor 10 are well known. With no bias applied to conductive gate 14, back-to-back p-n junctions exist between drain region 20 and source channel region 18 such that the current flow from drain region 20 to source region 18 is negligible. If, however, a positive bias is applied to conductive gate 14, mobile carriers within channel region 22 of p-type substrate 12 are repelled from the surface leaving behind a depletion region of uncompensated donor ions. If conductive gate 14 is further biased, minority carriers (i.e. electrons) are attracted to channel region 22 of substrate 12 to form a conductive inversion region near the upper surface of semiconductor substrate 12 in channel region 22. The bias required to induce an electron concentration near the surface of substrate 12 approximately equal to the whole concentration in the bulk of semiconductor substrate 12 is referred to as the threshold voltage (V.sub.t). With a threshold voltage V.sub.t applied to conductive gate 14, the conductive channel in channel region 22 permits current flow from drain region 20 to source region 18 if an appropriate bias is applied between drain region 20 and source region 18. For small values of drain voltage V.sub.d (i.e. V.sub.d &lt;V.sub.g -V.sub.t) the current (I.sub.ds) that flows from drain region 20 to source region 18 varies approximately linearly with the drain voltage V.sub.d. For large values of drain voltage (i.e. V.sub.d &gt;V.sub.g -V.sub.t), I.sub.ds is independent of V.sub.d to a first order approximation. Applying a gate voltage V.sub.t that is less than the threshold voltage V.sub.t induces a weak inversion region in channel region 22 of semiconductor substrate 12 permitting a small but measurable subthreshold current to flow from source to drain. Subthreshold currents are particularly important (and undesirable) in low voltage, low power applications such as MOS integrated circuits because of the large number of transistors in the integrated circuit and because the subthreshold region determines the manner in which the transistors turn on and off.
MOS transistors may be broadly characterized as either short channel or long channel devices. In a long channel device, the sub-threshold current is independent of the drain voltage, the threshold voltage is independent of the channel length and the transistor biasing, and the drain current in the saturation region is independent of the drain voltage. It will be appreciated that these characteristics of long channel devices are desirable from a manufacturing and circuit design perspective because of their tendency to minimize subthreshold currents and threshold voltage variation among transistors of varying dimensions. In contrast to long channel devices, short channel devices are characterized by a subthreshold current that varies with drain voltage, a threshold voltage that varies with channel length and biasing conditions, and a failure of current saturation in the saturation region. The following useful equation predicts the minimum channel length that can be expected to result in long channel behavior for a given set of process parameters: EQU L.sub.min =0.4[(x)(d)(W.sub.S +W.sub.D)).sup.2 ].sup.1/3
where x is the junction depth, d is the oxide thickness, and W.sub.S +W.sub.D is the sum of the source and drain junction depletion widths. See S. M. Sze., Physics of Semiconductor Devices pp. 431-86 (John Wiley and Sons, 1981). From this equation, its is evident that smaller transistor devices require shallower junction depths to minimize sub-threshold effects.
It will be appreciated to those skilled in the art of semiconductor processing that the MOS transistor shown in and described with respect to FIG. 10 is formed with a single source/drain implant. It will be further appreciated that MOS transistor fabrication is commonly accomplished using a pair of source/drain implants in advanced semiconductor processes. In such dual implant processes, the second source/drain impurity distribution is characterized by a greater junction depth, a higher peak impurity concentration, and a lateral displacement from the transistor channel boundaries. By displacing the deeper and more heavily doped source/drain region from the transistor channel boundary, dual implant lightly doped drain (LDD) transistors beneficially reduce the maximum electric field occurring within the transistor channel region. The critical junction depth for purposes of determining L.sub.min is the junction depth of the LDD regions. It is therefore desirable to minimize the junction depth of the LDD regions in LDD transistors.
Minimization of LDD junction depth is complicated by the dual implant process. The dual implant process is commonly achieved by implanting the LDD region using the transistor gate as an implant mask, forming spacer structures on sidewalls of the transistor gate, and implanting the heavily doped regions using the combined gate/spacer structure as an implant mask. Unfortunately, the implant necessary to achieve the heavily doped source/drain regions typically produces significant damage to the silicon lattice. To alleviate or remove lattice damage after a medium or high energy implant and to activate the implanted ions so that they can participate in the conduction process, a high temperature anneal is generally performed following the heavily doped implant. In a process flow where the heavily doped implant is performed after the lightly doped implant, the anneal cycle undesirably redistributes the previously implanted lightly doped regions thereby undesirably increasing the LDD junction depth. To address the redistribution of the lightly doped regions, some semiconductor processes follow a sequence in which the heavily doped implant is performed first with the spacer structures intact upon the sidewalls of the conductive gate. Thereafter, the spacer structures are removed with a wet or dry etch process so that the LDD implant will be aligned with the sidewalls of the conductive gate. Although this sequence addresses the redistribution of the LDD region, the removal of the spacer structure is difficult, if not impossible, to achieve without some degradation of gate oxide quality. More specifically, spacer structures are typically comprised of a deposited oxide and, as is well known, gate dielectrics are typically comprised of a thermal oxide. Because the composition of the gate dielectric and the spacer structures are quite similar and because of the proximity of the spacer structure to the gate dielectric, complete removal of the spacer structures cannot typically be accomplished without some inadvertent removal of the gate oxide at the perimeters of the transistor channels. In the age of deep sub-micron transistors and thin (i.e., less than 50 angstroms) gate oxides, the quality of the gate dielectric cannot be compromised without significantly degrading the quality of the overall integrated circuit. Accordingly, it is highly desirable to implement a process flow in which an LDD junction depth can be minimized without compromising the quality of the gate dielectric.